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Memoirs of the Graduate Schools of Engineering and System Informatics Kobe University, No. 8, pp. 000-000, 2016
doi:10.5047/gseku.e.2016.002

A novel test scheme for detecting faulty recall margin cells for 6T-4C FeRAM

Yohei UNEKI1, Shintaro IZUMI1, Hiroto KITAHARA1, Tomoki NAKAGAWA1, Koji YANAGIDA1, Shusuke YOSHIMOTO2, Hiroshi KAWAGUCHI3, Masahiko YOSHIMOTO1, Hiromitsu KIMURA4, Kyoji MARUMOTO4, Takaaki FUCHIKAMI4 and Yoshikazu FUJIMORI4

1Graduate School of System Informatics, Department of Infomation Science, Kobe University
2Osaka University
3Graduate School of Science, Technology and innovation, Kobe University
4Rohm Co. Ltd.

(Received January 30, 2017; Accepted February 7, 2017; Online published February 13, 2017)

Keywords: FeRAM, Memory Testing, Non-volatile Memory, Recall Margin.

This paper proposes a novel test scheme that can detect faulty margin cells in non-volatile 6T-4C FeRAM (six-transistor four-capacitor ferroelectric random access memory). The FeRAM behaves as a non-volatile memory using spontaneous polarization characteristic of the ferroelectric capacitor. The datum is stored as a difference in the polarization direction, and is read out as potential difference of the polarization direction. The proposed test scheme can screen the faulty cells that have smaller recall margins by injecting offset voltage to the memory cell. The proposed scheme is evaluated by Monte Carlo simulations of 16,000 times. The proposed test scheme is possible to detect all fault cells by injecting the offset voltage of 100 mV in a 0.13 μm CMOS process.


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